SIC417CD-T1-E3【PDF 15/19 页】IC REG DL BCK/LINEAR SYNC 32MLPQ

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Sheet目录46

11页 12页 13页 14页 [15页]16页 17页 18页 19页

Vishay Siliconix

SiC417

Document Number: 69062

S10-1367-Rev. D, 14-Jun-10

www.vishay.com

across C

, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then

capacitive-coupled into the FB pin via capacitor C

Dropout Performance

The output voltage adjusts range for continuous-conduction

operation is limited by the fixed 250 ns (typical) minimum

off-time of the one-shot. When working with low input

voltages, the duty-factor limit must be calculated using

worst-case values for on and off times. The duty-factor

limitation is shown by the next equation.

The inductor resistance and MOSFET on-state voltage drops

must be included when performing worst-case dropout

duty-factor calculations.

System DC Accuracy (V

OUT

Controller)

Three factors affect V

OUT

accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line and

load, and the external resistor tolerance. The error

comparator off set is trimmed so that under static conditions

it trips when the feedback pin is 500 mV, 1 %.

The on-time pulse from the SiC417 in the design example is

calculated to give a pseudo-fixed frequency of 250 kHz.

Some frequency variation with line and load is expected.

This variation changes the output ripple voltage. Because

constant on-time converters regulate to the valley of the

output ripple, ?of the output ripple appears as a DC

regulation error. For example, if the output ripple is 50 mV

with V

= 6 V, then the measured DC output will be 25 mV

above the comparator trip point. If the ripple increases to

80 mV with V

= 25 V, then the measured DC output will be

40 mV above the comparator trip. The best way to minimize

this effect is to minimize the output ripple.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of trace

resistance between the inductor and output capacitor.

This trace resistance should be optimized so that at full load

the output droops to near the lower regulation limit. Passive

droop minimizes the required output capacitance because

the voltage excursions due to load steps are reduced as

seen at the load.

The use of 1 % feedback resistors contributes up to 1 %

error. If tighter DC accuracy is required, 0.1 % resistors

should be used.

The output inductor value may change with current. This will

change the output ripple and therefore will have a minor

effect on the DC output voltage. The output ESR also affects

the output ripple and thus has a minor effect on the DC

output voltage.

Switching Frequency Variations

The switching frequency will vary depending on line and load

conditions. The line variations are a result of fixed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

increases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net effect is that

frequency tends to falls slightly with increasing input voltage.

The switching frequency also varies with load current as a

result of the power losses in the MOSFETs and the inductor.

For a conventional PWM constant-frequency converter, as

load increases the duty cycle also increases slightly to

compensate for IR and switching losses in the MOSFETs

and inductor.

A constant on-time converter must also compensate for the

same losses by increasing the effective duty cycle (more

time is spent drawing energy from V

as losses increase).

The on-time is essentially constant for a given V

OUT

combination, to off set the losses the off-time will tend to

reduce slightly as load increases. The net effect is that

switching frequency increases slightly with increasing load.

Figure 14 - Virtual ESR Ramp Current

OUT

High-

side

Low-

side

DUTY =

ON(MIN)

x T

OFF(MAX)

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